• Understand architecture/micro-architecture of
the PCIe, DDR4/DDR5 system, define verification
architecture.
• Define the subsystem-level, SoC-level and
system-level verification plan with detailed test cases.
Review with architects, designers and validation
engineers.
• Build UVM testing environments and create
testbenches, generate complete test cases based on the
verification plan, Run simulations, analyze complex
issues and resolve them in a timely manner.
• Define functional coverage points. Debug test
cases and work with designers to achieve expected
functional and code coverage goals.
• Track verification progress, adjust the test
plan based on coverage analysis, provide final
verification report for sign-off, generate test vectors
and assist in silicon bring-up, debug, characterization
and production.
Qualifications
• Proactive, curious and eager to learn, great
attention to details, positive, and great teamwork.
• Bachelor or MS degree in Electric/Computer
Engineering or Science, 5 years of verification
experience.
• Track record that shows the ability to build up
complex UVM test environments independently, experience
in achieving verification coverage for product
development.
• Proficiency in UVM, System Verilog, and C/C++,
knowledge of Assertion-based formal verification,
expertise in PCIe, DDR4/5 system.