• Implementation: RTL design in Verilog, lint,
clock domain crossing (CDC) analysis, top level
integration, synthesis, timing analysis, timing closure,
DFT-related tasks, and related documentations.
• Verification: work with verification team on
planning and execution, simulation, debugging block and
system level simulations, formal verification.
• Flow and methodology: work in a dynamic and
interdisciplinary R&D group that influences and guides
Metasemi's technical direction by understanding and
contributing to flow and methodology development.
• Validation and production: work with validation
and production team in generating test plans and
implementing test vectors to ensure product quality and
robustness.
Qualifications
• Proactive, curious and eager to learn, great
attention to details, positive, and great teamwork.
• Bachelor's or Master's Degree in Electrical or
Computer Engineering, 5+ years of relevant
digital/ASIC/IC design experience.
• Significant experience with RTL coding in
Verilog, Significant experience with standard ASIC/FPGA
software tools (synthesis, simulation, equivalence
checking, static timing analysis).
• Strong knowledge of scripting, Linux/Unix
environment, thorough understanding of ASIC/FPGA design
flow, strong design and system knowledge.
• Successful past digital leadership roles,
self-starter and fast learner with excellent
interpersonal skills， Track record of driving technical
solutions across organizational boundaries and multiple
technical disciplines.
• Design for verification experience or
understanding (assertion-based design strategies, code
coverage, functional coverage, test plans etc.) would be
an asset, additional knowledge of Analog blocks for
behavior modelling and DDR protocols, experience with
PCIe and/or memory controller is a plus.